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CS2842A, CS3842A, CS2843A, CS3843A Off-Line Current Mode PWM Control Circuit with Undervoltage Lockout
The CS284XA, CS384XA provides all the necessary features to implement off-line fixed frequency current-mode control with a minimum number of external components. The CS384XA family incorporates a new precision temperature-controlled oscillator with an internally trimmed discharge current to minimize variations in frequency. A precision duty-cycle clamp eliminates the need for an external oscillator when a 50% duty-cycle is used. Duty-cycles greater than 50% are also possible. On board logic ensures that VREF is stabilized before the output stage is enabled. Ion implant resistors provide tighter control of undervoltage lockout. Other features include low startup current, pulse-by-pulse current limiting, and a high-current totem pole output for driving capacitive loads, such as the gate of power MOSFET. The output is LOW in the off state, consistent with N-channel devices. The CS384XA series of current-mode control ICs are available in 8 and14 lead packages for surface mount (SO) applications as well as 8 lead PDIP packages. Features * Optimized for Off-line Control * Internally Trimmed Temperature Compensated Oscillator * Maximum Duty-Cycle Clamp * VREF Stabilized Before Output Stage is Enabled * Low Startup Current * Pulse-By-Pulse Current Limiting * Improved Undervoltage Lockout * Double Pulse Suppression * 1.0% Trimmed Bandgap Reference * High Current Totem Pole Output
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8 DIP-8 N SUFFIX CASE 626 1 SO-8 D SUFFIX CASE 751 14 14 1 SO-14 D SUFFIX CASE 751A 1 x y A WL, L YY, Y WW, W = 2 or 3 = 2 or 3 = Assembly Location = Wafer Lot = Year = Work Week 1 CSx84yA AWLYWW 1 8 x84yA ALYWX x84yA AWL YYWW
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8 1
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
(c) Semiconductor Components Industries, LLC, 2006
July, 2006 - Rev. 4
1
Publication Order Number: CS2842A/D
CS2842A, CS3842A, CS2843A, CS3843A
PIN CONNECTIONS
DIP-8 & SO-8 COMP VFB Sense OSC 1 8 VREF VCC VOUT GND COMP NC VFB NC Sense NC OSC 1 SO-14 14 VREF NC VCC VCC Pwr VOUT Pwr GND GND
VCC 34 V
Undervoltage Lock-out Circuit Set/ Reset 5.0 V Reference Internal Bias Output Enable NOR
VCC Pwr
GND 16 V/10 V (8.4 V/7.6 V) 2.50 V
VREF
OSC
Oscillator
VOUT + VFB COMP Error Amplifier - VC 2R S R R 1.0 V Current Sensing Comparator PWM Latch Pwr GND
Sense
( ) Indicates CS2843A/3843A
Figure 1. Block Diagram
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CS2842A, CS3842A, CS2843A, CS3843A
MAXIMUM RATINGS*
Rating Supply Voltage (ICC < 30 mA) Supply Voltage (Low Impedance Source) Output Current Output Energy (Capacitive Load) Analog Inputs (VFB, Sense) Error Amp Output Sink Current Package Thermal Resistance, PDIP-8 Junction-to-Case, RJC Junction-to-Ambient, RJA Package Thermal Resistance, SO-8 Junction-to-Case, RJC Junction-to-Ambient, RJA Package Thermal Resistance, SO-14 Junction-to-Case, RJC Junction-to-Ambient, RJA Lead Temperature Soldering: 1. 10 second maximum. 2. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Wave Solder (through hole styles only) (Note 1) Reflow (SMD styles only) (Note 2) Value Self Limiting 30 1.0 5.0 -0.3 to + 5.5 10 52 100 45 165 30 125 260 peak 230 peak Unit - V A J V mA CW CW CW CW CW CW C C
VCC = 15 V*; RT = 680 , CT = 0.022 F for triangular mode, RT = 10 k, CT = 3.3 nF for sawtooth mode (see Figure 7); unless otherwise stated.) CS2842A/CS2843A Characteristic Reference Section Output Voltage Line Regulation Load Regulation Temperature Stability Total Output Variation Output Noise Voltage Long Term Stability Output Short Circuit Oscillator Section Initial Accuracy Voltage Stability Temperature Stability Amplitude Discharge Current Sawtooth Mode (see Figure 7), TJ = 25C Triangular Mode (see Figure 7), TJ = 25C 12 VCC 25 V Sawtooth Mode TMIN TA TMAX (Note 3.) Triangular Mode TMIN TA TMAX (Note 3.) OSC peak to peak TJ = 25C TMIN TA TMAX 47 47 - - - - 7.5 7.2 52 52 0.2 5.0 8.0 1.7 8.3 - 57 57 1.0 - - - 9.3 9.5 47 44 - - - - 7.5 7.2 52 52 0.2 5.0 8.0 1.7 8.3 - TJ = 25C, IOUT = 1.0 mA 12 VIN 25 V 1.0 IOUT 20 mA Note 3. Line, Load, Temperature (Note 3.) 10 Hz f 10 kHz, TJ = 25C (Note 3.) TA = 125C, 1.0 kHrs. (Note 3.) TA = 25C 4.95 - - - 4.90 - - -30 5.00 6.0 6.0 0.2 - 50 5.0 -100 5.05 20 25 0.4 5.10 - 25 -180 4.90 - - - 4.82 - - -30 5.00 6.0 6.0 0.2 - 50 5.0 -100 Test Conditions Min Typ Max
ELECTRICAL CHARACTERISTICS (-25 TA 85 for CS2842A/CS2843A, 0 TA 70 for CS3842A/CS3843A.
CS3842A/CS3843A Min Typ Max Unit
5.10 20 25 0.4 5.18 - 25 -180
V mV mV mV/C V V mV mA
57 60 1.0 - - - 9.3 9.5
kHz kHz % % % V mA mA
3. These parameters, although guaranteed, are not 100% tested in production. *Adjust VCC above the start threshold before setting at 15 V.
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CS2842A, CS3842A, CS2843A, CS3843A
ELECTRICAL CHARACTERISTICS (continued) (-25 TA 85 for CS2842A/CS2843A, 0 TA 70 for CS3842A/CS3843A.
VCC = 15 V*; RT = 680 , CT = 0.022 F for triangular mode, RT = 10 k, CT = 3.3 nF for sawtooth mode (see Figure 7); unless otherwise stated.) CS2842A/CS2843A Characteristic Error Amp Section Input Voltage Input Bias Current AVOL Unity Gain Bandwidth PSRR Output Sink Current Output Source Current VOUT High VOUT Low Current Sense Section Gain Maximum Input Signal PSRR Input Bias Current Delay to Output Output Section Output Low Level Output High Level Rise Time Fall Time Output Leakage Total Standby Current Startup Current Operating Supply Current VCC Zener Voltage - VFB = VSENSE = 0 V, RT = 10 k, CT = 3.3 nF ICC = 25 mA - 11 - 0.5 17 34 1.0 - - - 11 - 0.5 17 34 ISINK = 20 mA ISINK = 200 mA ISOURCE = 20 mA ISOURCE = 200 mA TJ = 25C, CL = 1.0 nF (Note 4.) TJ = 25C, CL = 1.0 nF (Note 4.) UVLO Active, VOUT = 0 - - 13 12 - - - 0.1 1.5 13.5 13.5 50 50 -0.01 0.4 2.2 - - 150 150 -10.00 - - 13 12 - - - 0.1 1.5 13.5 13.5 50 50 -0.01 Notes 5 & 6. VCOMP = 5.0 V (Note 5.) 12 VCC 25 V (Note 5.) VSENSE = 0 TJ = 25C (Note 4.) 2.85 0.9 - - - 3.00 1.0 70 -2.0 150 3.15 1.1 - -10 300 2.85 0.9 - - - 3.00 1.0 70 -2.0 150 VCOMP = 2.5 V VFB = 0 2.0 VOUT 4.0 V Note 4. 12 VCC 25 V VFB = 2.7 V, VCOMP = 1.1 V VFB = 2.3 V, VCOMP = 5.0 V VFB = 2.3 V, 15 k to ground VFB = 2.7 V, 15 k to VREF 2.45 - 65 0.7 60 2.0 -0.5 5.0 - 2.50 -0.3 90 1.0 70 6.0 -0.8 6.0 0.7 2.55 -1.0 - - - - - - 1.1 2.42 - 65 0.7 60 2.0 -0.5 5.0 - 2.50 -0.3 90 1.0 70 6.0 -0.8 6.0 0.7 Test Conditions Min Typ Max
CS3842A/CS3843A Min Typ Max Unit
2.58 -2.0 - - - - - - 1.1
V A dB MHz dB mA mA V V
3.15 1.1 - -10 300
V/V V dB A ns
0.4 2.2 - - 150 150 -10.00
V V V V ns ns A
1.0 - -
mA mA V
4. These parameters, although guaranteed, are not 100% tested in production. 5. Parameters measured at trip point of latch with VFB = 0. 6. Gain defined as: A = VCOMP/VSENSE; 0 VSENSE 0.8 V. *Adjust VCC above the start threshold before setting at 15 V.
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CS2842A, CS3842A, CS2843A, CS3843A
VCC = 15 V*; RT = 680 , CT = 0.022 F for triangular mode, RT = 10 k, CT = 3.3 nF for sawtooth mode (see Figure 7); unless otherwise stated.) CS2842A Characteristic Start Threshold Min. Operating Voltage Test Conditions - After Turn On Min Typ Max Min CS3842A Typ Max
ELECTRICAL CHARACTERISTICS (continued) (-25 TA 85 for CS2842A/CS2843A, 0 TA 70 for CS3842A/CS3843A.
CS2843A/CS3843A Min Typ Max Unit V V
Undervoltage Lockout Section 15 9.0 16 10 17 11 14.5 8.5 16 10 17.5 11.5 7.8 7.0 8.4 7.6 9.0 8.2
*Adjust VCC above the start threshold before setting at 15 V.
PACKAGE PIN DESCRIPTION
Package Pin Number DIP-8 1 2 3 4 5 SO-8 1 2 3 4 5 SO-14 1 3 5 7 8 9 Symbol COMP VFB Description
Frequency (kHz)
Duty Cycle (%) .002 .003 .005 CT (F) .01 .02 .03 .04 .05
100
200
300 400 500
700
RT ()
Figure 2. Oscillator Frequency vs. CT
Figure 3. Oscillator Duty Cycle vs. RT
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10 k
1k
2k
3k 4k 5k
7k
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Error amp output, used to compensate error amplifier. Error amp inverting input. Sense OSC Noninverting input to Current Sense Comparator. Oscillator timing network with capacitor to ground, resistor to VREF. Ground. Output driver ground. Output drive pin. GND - 6 - 6 Pwr GND VOUT VCC NC 10 11 - 7 8 - 7 8 VCC Pwr VREF Output driver positive supply. Positive power supply. 12 14 Output of 5.0 V internal reference. No connection. - - 2, 4, 6, 13
TYPICAL PERFORMANCE CHARACTERISTICS
900 800 700 600 500 400 300 200 100 .0005 .001 RT = 10 k RT = 1.5 k RT = 680
100 90 80 70 60 50 40 30 20 10
CS2842A, CS3842A, CS2843A, CS3843A
VREF RT 2N2222 4.7 k 100 k 1.0 k ERROR AMP ADJUST 4.7 k COMP VFB 5.0 k Sense ADJUST Sense OSC VREF 0.1 F VCC VOUT GND 1.0 k 1.0 W 0.1 F VOUT A VCC
GND CT
Figure 4. Test Circuit
CIRCUIT DESCRIPTION
VCC OSC OSC RESET EA Output Switch Current VCC ICC < 15 mA < 1.0 mA VON VOFF VCC IO
ON/OFF Command to reset of IC CSX842A VON VOFF 16 V 10 V CSX843A 8.4 V 7.6 V
VO
Figure 6. Timing Diagram for Key CS2841B Parameters
Figure 5. Typical Undervoltage Characteristics Undervoltage Lockout
During Undervoltage Lockout (Figure 5), the output driver is biased to a high impedance state. The output should be shunted to ground with a resistor to prevent output leakage current from activating the power switch.
PWM Waveform
When the power supply sees a sudden large output current increase, the control voltage will increase allowing the duty cycle to momentarily increase. Since the duty cycle tends to exceed the maximum allowed to prevent transformer saturation in some power supplies, the internal oscillator waveform provides the maximum duty cycle clamp as programmed by the selection of oscillator components.
Setting the Oscillator
To generate the PWM waveform, the control voltage from the error amplifier is compared to a current sense signal which represents the peak output inductor current (Figure 6). An increase in VCC causes the inductor current slope to increase, thus reducing the duty cycle. This is an inherent feed-forward characteristic of current mode control, since the control voltage does not have to change during changes of input supply voltage.
Oscillator timing capacitor, CT, is charged by VREF through RT and discharged by an internal current source. During the discharge time, the internal clock signal blanks out the output to the Low state, thus providing a user selected maximum duty cycle clamp. Charge and discharge times are determined by the formula:
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CS2842A, CS3842A, CS2843A, CS3843A
V * Vlower tc + RTCT ln REF VREF * Vupper V * IdRT * Vlower td + RTCT ln REF VREF * IdRT * Vupper
VREF RT OSC CT GND
Substituting in typical values for the parameters in the above formulas: VREF = 5.0 V Vupper = 2.7 V Vlower = 1.0 V Id = 8.3 mA tc 0.5534RTCT
2.3 * 0.0083RT td + RTCT ln 4.0 * 0.0083RT
Timing Parameters Vupper
The frequency and maximum duty cycle can be determined using the Typical Performance Characteristic graphs.
Grounding
Vlower tc Sawtooth Mode Large RT ( 10 k) VOSC td
High peak currents associated with capacitive loads necessitate careful grounding techniques. Timing and bypass capacitors should be connected close to GND pin in a single point ground. The transistor and 5.0 k potentiometer, shown in the test circuit, are used to sample the oscillator waveform and apply and adjustable ramp to Sense.
Internal Clock Triangular Mode Small RT ( 700 k) VOSC
Internal Clock
Figure 7. Oscillator Timing Network and Parameters
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CS2842A, CS3842A, CS2843A, CS3843A
ORDERING INFORMATION
Device CS2842ALN8 CS2843ALN8 CS2842ALD14 CS2842ALDR14 CS3842AGN8 CS3842AGD8 CS3842AGDR8 CS3842AGD14 CS3842AGDR14 CS3843AGN8 CS3843AGD8 CS3843AGDR8 CS3843AGD14 CS3843AGDR14 0C to 70C -25C to 85C Temperature Range Package DIP-8 DIP-8 SO-14 SO-14 DIP-8 SO-8 SO-8 SO-14 SO-14 DIP-8 SO-8 SO-8 SO-14 SO-14 Shipping 50 Units/Rail 50 Units/Rail 55 Units/Rail 2500 Tape & Reel 50 Units/Rail 98 Units/Rail 2500 Tape & Reel 55 Units/Rail 2500 Tape & Reel 50 Units/Rail 98 Units/Rail 2500 Tape & Reel 55 Units/Rail 2500 Tape & Reel
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CS2842A, CS3842A, CS2843A, CS3843A
PACKAGE DIMENSIONS
DIP-8 N SUFFIX CASE 626-05 ISSUE L
NOTES: 1. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 2. PACKAGE CONTOUR OPTIONAL (ROUND OR SQUARE CORNERS). 3. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 9.40 10.16 6.10 6.60 3.94 4.45 0.38 0.51 1.02 1.78 2.54 BSC 0.76 1.27 0.20 0.30 2.92 3.43 7.62 BSC --- 10_ 0.76 1.01 INCHES MIN MAX 0.370 0.400 0.240 0.260 0.155 0.175 0.015 0.020 0.040 0.070 0.100 BSC 0.030 0.050 0.008 0.012 0.115 0.135 0.300 BSC --- 10_ 0.030 0.040
8
5
-B-
1 4
F
NOTE 2
-A-
L
C -T-
SEATING PLANE
J N D K
M
M TA
M
H
G 0.13 (0.005) B
M
SO-8 D SUFFIX CASE 751-07 ISSUE W
-X- A
8 5 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D G H J K M N S MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
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CS2842A, CS3842A, CS2843A, CS3843A
PACKAGE DIMENSIONS
SO-14 D SUFFIX CASE 751A-03 ISSUE F
-A-
14 8
-B-
1 7
P 7 PL 0.25 (0.010)
M
B
M
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
G
C
R X 45 _
F
-T-
SEATING PLANE
D 14 PL 0.25 (0.010)
K
M
M
S
J
TB
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.55 8.75 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.19 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 0_ 7_ 0.228 0.244 0.010 0.019
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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CS2842A/D

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